SH7641 Datasheet, PDF (235/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 7 Cache
Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Instruction
Cache
Locking
Mode Bit
W3LOAD
W3LOCK
W2LOAD
W2LOCK
Way to be Replaced
0
*
*
*
*
Decided by LRU (table 7.3)
1
*
0
*
0
Decided by LRU (table 7.3)
1
*
0
0
1
Decided by LRU (table 7.6)
1
0
1
*
0
Decided by LRU (table 7.7)
1
0
1
0
1
Decided by LRU (table 7.8)
1
0
*
1
1
Way 2
1
1
1
0
*
Way 3
[Legend]
* : Don't care
Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
Table 7.5 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction
Cache
Locking
Mode Bit
W3LOAD
W3LOCK
W2LOAD
W2LOCK
Way to be Replaced
0
*
*
*
*
Decided by LRU (table 7.3)
1
*
0
*
0
Decided by LRU (table 7.3)
1
*
0
*
1
Decided by LRU (table 7.6)
1
*
1
*
0
Decided by LRU (table 7.7)
1
*
1
*
1
Decided by LRU (table 7.8)
[Legend]
* : Don't care
Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
Table 7.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0)
LRU (Bits 5 to 0)
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
1
0
Rev. 4.00 Sep. 14, 2005 Page 185 of 982
REJ09B0023-0400