SH7641 Datasheet, PDF (368/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
6

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
5
CKS2
0
R/W Clock Select
4
CKS1
0
R/W Select the clock input to count-up the refresh timer
3
CKS0
0
R/W ^{counter (RTCNT).}
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
2
RRC2
0
R/W Refresh Count
1
RRC1
0
R/W Specify the number of continuous refresh cycles, when
0
RRC0
0
R/W ^{the refresh request occurs after the coincidence of the}
values of the refresh timer counter (RTCNT) and the
refresh time constant register (RTCOR). These bits
can make the period of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
Rev. 4.00 Sep. 14, 2005 Page 318 of 982
REJ09B0023-0400