SH7641 Datasheet, PDF (764/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.9 FIFO Control Register (SCFCR)
The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO
registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.
Bit
Bit Name
15 to 11 —
10
RSTRG2
9
RSTRG1
8
RSTRG0
Initial
value
All 0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RTS Output Active Trigger
R/W When the quantity of receive data in receive FIFO
R/W
register (SCFRDR) becomes more than the number
shown below, RTS signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Note:
Set the trigger number to 1 when the receive
data is transferred by the DMAC in
synchronous mode. If the set trigger number is
other than 1, the receive data remains in
SCFRDR should be read by the CPU.
Rev. 4.00 Sep. 14, 2005 Page 714 of 982
REJ09B0023-0400