SH7641 Datasheet, PDF (349/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1
HW1
0
R/W Delay Cycles from RD, WEn Negation to Address,
0
HW0
0
R/W ^{CSn Negation}
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS6BWCR
Bit
Bit Name
31 to 21 
Initial
Value
All 0
20
BAS
0
19 to 13 
All 0
12
SW1
0
11
SW0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Byte-Selection SRAM Byte Access Selection
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Delay Cycles from Address, CSn Assertion
R/W ^{to RD, WEn Assertion}
Specify the number of delay cycles from address, CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 4.00 Sep. 14, 2005 Page 299 of 982
REJ09B0023-0400