SH7641 Datasheet, PDF (145/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction
Instruction Code
DCT PSTS MACL,Dz 111110**********
110111100000zzzz
DCF PSTS MACL,Dz 111110**********
110111110000zzzz
PLDS Dz,MACH 111110**********
111011010000zzzz
DCT PLDS Dz,MACH 111110**********
111011100000zzzz
DCF PLDS Dz,MACH 111110**********
111011110000zzzz
PLDS Dz,MACL 111110**********
111111010000zzzz
DCT PLDS Dz,MACL 111110**********
111111100000zzzz
DCF PLDS Dz,MACL 111110**********
111111110000zzzz
PADDC Sx,Sy,Dz 111110**********
10110000xxyyzzzz
PSUBC Sx,Sy,Dz 111110**********
10100000xxyyzzzz
PCMP Sx,Sy
111110**********
10000100xxyy0000
PABS Sx,Dz
111110**********
10001000xx00zzzz
PABS Sy,Dz
111110**********
1010100000yyzzzz
PRND Sx,Dz
111110**********
10011000xx00zzzz
PRND Sy,Dz
111110**********
1011100000yyzzzz
Note: * See table 2.32.
Operation
If DC = 1, MACL → Dz
Execution
States DC
1

If DC = 0, MACL → Dz 1

Dz → MACH
1

If DC = 1, Dz → MACH 1

If DC = 0, Dz → MACH 1

Dz → MACL
1

If DC = 1, Dz → MACL 1

If DC = 0, Dz → MACL 1

Sx + Sy + DC → Dz
1
Carry → DC
Sx – Sy – DC → Dz
1
Borrow → DC
Sx – Sy → DC update* 1
Carry
Borrow
*
If Sx < 0, 0 – Sx → Dz 1
*
If Sx > = 0, nop
If Sy < 0, 0 – Sy → Dz 1
*
If Sx > = 0, nop
Sx + h'00008000 → Dz 1
*
LSW of Dz → h'0000
Sy + h'00008000 → Dz 1
*
LSW of Dz → h'0000
Rev. 4.00 Sep. 14, 2005 Page 95 of 982
REJ09B0023-0400