SH7641 Datasheet, PDF (362/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Burst ROM (Clock Synchronous):
• CS0WCR
Bit
Bit Name
31 to 18 
17
BW1
16
BW0
15 to 11 
Initial
Value
All 0
0
0
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Burst Wait Cycles
R/W Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 312 of 982
REJ09B0023-0400