SH7641 Datasheet, PDF (857/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 21 A/D Converter
Typical operations when three channels in A/D0 (AN0 to AN2) are selected in multi mode are
described next. Figure 21.3 shows a timing diagram for this example.
1. Multi mode is selected (MULTI = 1), channel group A/D0 is selected, analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA0.
3. Next, conversion of the second channel (AN1) starts automatically.
4. Conversion proceeds in the same way through the third channel (AN2).
5. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI0 interrupt is requested at this
time.
ADST
ADF
Set*
A/D conversion
Clear
Clear*
Channel 0 (AN0)
operating
Channel 1 (AN1)
operating
Channel 2 (AN2)
operating
Channel 3 (AN3)
operating
ADDRA
Waiting
A/D conversion 1
Waiting
Waiting
A/D conversion 2
Waiting
Waiting
A/D conversion 3
Waiting
Transfer
A/D conversion result 1
Waiting
ADDRB
A/D conversion result 2
ADDRC
A/D conversion result 3
ADDRD
Note: * Vertical arrows ( ) indicate instruction execution by software.
Figure 21.3 Example of A/D Converter Operation
(Multi Mode, Channels AN0 to AN2 Selected)
Rev. 4.00 Sep. 14, 2005 Page 807 of 982
REJ09B0023-0400