SH7641 Datasheet, PDF (156/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
39 31
0 39 31
0
Guard Soruce 1
Guard Source 2
ALU
GT Z N V DC
DSR
Ignored
Guard Destination
Cleared
39 31
0
Figure 3.7 ALU Logical Operation Flow
Table 3.4 Variation of ALU Logical Operations
Mnemonic
PAND
POR
PXOR
Function
Logical AND
Logical OR
Logical exclusive OR
Source 1
Sx
Sx
Sx
Source 2
Sy
Sy
Sy
Destination
Dz
Dz
Dz
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of the DC bit is selected by the CS0 to CS2 (condition selection)
bits in DSR. The DC bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
The DC bit is always cleared.
2. Negative Value Mode: CS[2:0] = 001
Bit 31 of the operation result is loaded into the DC bit.
3. Zero Value Mode: CS[2:0] = 010
The DC bit is set when the operation result is zero; otherwise it is cleared.
4. Overflow Mode: CS[2:0] = 011
The DC bit is always cleared.
Rev. 4.00 Sep. 14, 2005 Page 106 of 982
REJ09B0023-0400