SH7641 Datasheet, PDF (304/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 11 User Break Controller (UBC)
11.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2¹² – 1 times. When a break condition is satisfied, it decreases BETR. A
break is issued when the break condition is satisfied after BETR becomes H'0001.
Bit
Bit Name
15 to 12 
Initial
Value
All 0
11 to 0 BET11 to All 0
BET0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Execution Times
11.2.11 Branch Source Register (BRSR)
BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source
instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on
reset. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue
structure and a stored register is shifted at every branch.
Initial
Bit
Bit Name Value
31
SVF
0
30 to 28 
All 0
27 to 0 BSA27 to 
BSA0
R/W Description
R BRSR Valid Flag
Indicates whether the branch source address is stored.
When a branch source address is fetched, this flag is
set to 1. This flag is cleared to 0 by reading from
BRSR.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid
R Reserved
These bits are always read as 0. The write value
should always be 0.
R Branch Source Address
Store bits 27 to 0 of the branch source address.
Rev. 4.00 Sep. 14, 2005 Page 254 of 982
REJ09B0023-0400