SH7641 Datasheet, PDF (321/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

BSC functional block diagram is shown in figure 12.1.
Section 12 Bus State Controller (BSC)
BACK
BREQ
Bus
mastership
controller
CMNCR
WAIT
CS0, CS2, CS3,
CS4, CS5A, CS5B,
CS6A, CS6B
MD3
Wait
controller
Area
controller
CS0WCR
CS6BWCR
RWTCNT
CS0BCR
CS6BBCR
A25 to A0,
D31 to D0
BS, RD/WR,
RD, WE3 to WE0,
RASU, RASL,
CASU, CASL
CKE, DQMxx, AH,
FRAME
Memory
controller
Refresh
controller
SDCR
RTCSR
RTCNT
Comparator
RTCOR
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
RWTCNT: Reset wait counter
CSnBCR: CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
BSC
Figure 12.1 BSC Functional Block Diagram
Rev. 4.00 Sep. 14, 2005 Page 271 of 982
REJ09B0023-0400