SH7641 Datasheet, PDF (126/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Shift Instructions
Table 2.22 Shift Instructions
Instruction
ROTL
Rn
ROTR
Rn
ROTCL Rn
ROTCR Rn
SHAD
Rm,Rn
Instruction Code
0100nnnn00000100
0100nnnn00000101
0100nnnn00100100
0100nnnn00100101
0100nnnnmmmm1100
SHAL
SHAR
SHLD
Rn
Rn
Rm,Rn
0100nnnn00100000
0100nnnn00100001
0100nnnnmmmm1101
SHLL
Rn
SHLR
Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
0100nnnn00000000
0100nnnn00000001
0100nnnn00001000
0100nnnn00001001
0100nnnn00011000
0100nnnn00011001
0100nnnn00101000
0100nnnn00101001
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm →
[MSB → Rn]
T ← Rn ← 0
MSB → Rn → T
Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm →
[0 → Rn]
T ← Rn ← 0
0 → Rn → T
Rn << 2 → Rn
Rn >> 2 → Rn
Rn << 8 → Rn
Rn >> 8 → Rn
Rn << 16 → Rn
Rn >> 16 → Rn
Execution
States
1
1
1
1
1
T Bit
MSB
LSB
MSB
LSB
—
1
MSB
1
LSB
1
—
1
MSB
1
LSB
1
—
1
—
1
—
1
—
1
—
1
—
Rev. 4.00 Sep. 14, 2005 Page 76 of 982
REJ09B0023-0400