SH7641 Datasheet, PDF (443/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC
Dual Address Mode for the SDRAM Interface
BSC Register Setting
CSnBCR CS3WCR. CS3WCR.
Idle
WTRP TRWL Read to
Setting Setting Setting Read
0
0
0
1/1/1/2
0
0
1
1/1/1/2
0
0
2
1/1/1/2
0
0
3
1/1/1/2
0
1
0
2/2/2/2
0
1
1
2/2/2/2
0
1
2
2/2/2/2
0
1
3
2/2/2/2
0
2
0
3/3/3/3
0
2
1
3/3/3/3
0
2
2
3/3/3/3
0
2
3
3/3/3/3
0
3
0
4/4/4/4
0
3
1
4/4/4/4
0
3
2
4/4/4/4
0
3
3
4/4/4/4
1
0
0
2/2/2/2
1
0
1
2/2/2/2
1
0
2
2/2/2/2
1
0
3
2/2/2/2
1
1
0
2/2/2/2
1
1
1
2/2/2/2
1
1
2
2/2/2/2
1
1
3
2/2/2/2
1
2
0
3/3/3/3
1
2
1
3/3/3/3
1
2
2
3/3/3/3
CPU Access
Write to
Write
1/1/2/3
1/1/2/3
2/2/2/3
3/3/3/3
1/1/2/3
2/2/2/3
3/3/3/3
4/4/4/4
2/2/2/3
3/3/3/3
4/4/4/4
5/5/5/5
3/3/3/3
4/4/4/4
5/5/5/5
6/6/6/6
1/1/2/3
1/1/2/3
2/2/2/3
3/3/3/3
1/1/2/3
2/2/2/3
3/3/3/3
4/4/4/4
2/2/2/3
3/3/3/3
4/4/4/4
Read to
Write
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
4/4/4/5
4/4/4/5
4/4/4/5
4/4/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
Write to
Read
0/0/0/0
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
4/4/4/4
5/5/5/5
3/3/3/3
4/4/4/4
5/5/5/5
6/6/6/6
1/1/1/1
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
4/4/4/4
DMAC Access
Read to Write to
Write Read
2
0
2
1
2
2
2
3
2
1
2
2
2
3
2
4
3
2
3
3
3
4
3
5
4
3
4
4
4
5
4
6
2
1
2
1
2
2
2
3
2
1
2
2
2
3
2
4
3
2
3
3
3
4
Rev. 4.00 Sep. 14, 2005 Page 393 of 982
REJ09B0023-0400