SH7641 Datasheet, PDF (581/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
• TIORL_0, TIORL_3, TIORL_4
Initial
Bit
Bit Name value R/W
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
Description
I/O Control D3 to D0
Specify the function of TGRD.
When TGRD is used as the buffer register of TGRB,
this setting is disabled, and input capture/output
compare does not occur.
See the following tables.
TIORL_0: Table 18.11
TIORL_3: Table 18.15
TIORL_4: Table 18.17
I/O Control C3 to C0
Specify the function of TGRC.
When TGRC is used as the buffer register of TGRA,
this setting is disabled, and input capture/output
compare does not occur.
See the following tables.
TIORL_0: Table 18.19
TIORL_3: Table 18.23
TIORL_4: Table 18.25
Rev. 4.00 Sep. 14, 2005 Page 531 of 982
REJ09B0023-0400