SH7641 Datasheet, PDF (605/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Bit
7
6
5 to 3
2
1
0
Bit Name
SYNC4
SYNC3
Initial
value
0
0

All 0
SYNC2
0
SYNC1
0
SYNC0
0
R/W Description
R/W Timer Synchro 4 and 3
R/W These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit , the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_4 and TCNT_3 operate independently (TCNT
presetting/clearing is unrelated to other channels)
1: TCNT_4 and TCNT_3 performs synchronous
operation
TCNT synchronous presetting/synchronous clearing is
possible
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Timer Synchro 2 to 0
R/W These bits are used to select whether operation is
R/W ^{independent of or synchronized with other channels.}
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit , the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently (TCNT
presetting /clearing is unrelated to other channels).
1: TCNT_2 to TCNT_0 performs synchronous
operation. TCNT synchronous
presetting/synchronous clearing is possible.
Rev. 4.00 Sep. 14, 2005 Page 555 of 982
REJ09B0023-0400