SH7641 Datasheet, PDF (289/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
Program
execution state
Interrupt
No
generated?
Yes
No
SR.BL=0
or sleep mode?
Yes
NMI?
Yes
Yes
Set interrupt sourse in
INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/RB
bits in SR to1
Branch to exception
handler
No
Level 15
No
interrupt?
Yes
Level 14
No
interrupt?
I3 to I0 level
14or lower?
No
Yes
Yes
I3 to I0 level
13 or lower?
Level 1
No
interrupt?
Yes
No
Yes
I3 to I0
level 0?
No
I3 to I0: Interrupt mask bits in status register (SR)
Figure 10.2 Interrupt Operation Flowchart
Rev. 4.00 Sep. 14, 2005 Page 239 of 982
REJ09B0023-0400