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SH7641 Datasheet, PDF (861/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series
Section 21 A/D Converter
ADCSR
write cycle
Pφ
Address
Write
signal
Input sampling
timing
ADCSR address
ADF
tD
tSPL
[Legend]
tD : A/D conversion start delay
tSPL : Input sampling time
tCONV : A/D conversion time
tCONV
Figure 21.5 A/D Conversion Timing
Table 21.3 A/D Conversion Time (Single Mode)
CKS1 = 1, CKS0 = 1 CKS1 = 1, CKS0 = 1
Symbol Min. Typ. Max. Min. Typ. Max.
A/D conversion tD
start delay
18
—
21
10
—
13
Input sampling
tSPL
time
—
129 —
—
65
—
A/D conversion tCONV
time
535 —
545 275 —
285
Note: Values in the table are numbers of states (tcyc).
CKS1 = 1, CKS0 = 1
Min. Typ. Max.
6
—
9
—
33
—
141 —
151
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1
0
1
CKS0
0
1
0
1
Conversion Time (tcyc)
128 (constant)
256 (constant)
512 (constant)
Reserved
Rev. 4.00 Sep. 14, 2005 Page 811 of 982
REJ09B0023-0400