SH7641 Datasheet, PDF (271/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.2 Input/Output Pins
Table 10.1 shows the INTC pin configuration.
Table 10.1 Pin Configuration
Name
Abbreviation I/O Description
Nonmaskable interrupt input pin NMI
Input Input of interrupt request signal, not
maskable by the interrupt mask bits in
SR
Interrupt input pins
IRQ7 to IRQ0 Input Input of interrupt request signals,
maskable by the interrupt mask bits in
SR
10.3 Register Descriptions
The INTC has the following registers. For details on register addresses and register states during
each processing, refer to section 24, List of Registers.
• Interrupt control register 0 (ICR0)
• Interrupt control register 1 (ICR1)
• Interrupt control register 3 (ICR3)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register J (IPRJ)
• Interrupt request register 0 (IRR0)
• Interrupt mask register 0 (IMR0)
• Interrupt mask register 1 (IMR1)
• Interrupt mask register 2 (IMR2)
• Interrupt mask register 3 (IMR3)
• Interrupt mask register 4 (IMR4)
• Interrupt mask register 5 (IMR5)
Rev. 4.00 Sep. 14, 2005 Page 221 of 982
REJ09B0023-0400