SH7641 Datasheet, PDF (184/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
R8 [Ix]
R4 [Ax]
+2 (INC)
+0 (Not update)
R5 [Ax]
ALU
+2 (INC)
+0 (Not update)
Additional
adder for DSP
addressing
Three address operation types:
1. Not update
2. Add-index-register (Ix/Iy)
3. Increment
All operations are post-update type.
To decrement an address pointer, set –2 in an index register.
R9 [Iy]
R6 [Ay]
R7 [Ay]
AU
Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.W
Addressing in X and Y data transfer operation is always word mode; that is access to X and Y data
memories are 16-bit data width. Therefore, the increment operation adds 2 to an address register.
To realize decrement, set –2 in an index register and use add-index-register operation.
Addressing for MOVS: This LSI has single-data transfer instructions (MOVS.W and MOVS.L)
to load/store DSP data registers. In these instructions, R2 to R5 (As: Address register for single-
data transfer) are used for the address pointer.
There are four data addressing types for single-data transfer operation.
1. Not-update address register
2. Add-index register (post-update)
3. Increment address register (post-update)
4. Decrement address register (pre-update)
The address pointer set As has an index register R8[Is] (figure 3.20)
Rev. 4.00 Sep. 14, 2005 Page 134 of 982
REJ09B0023-0400