SH7641 Datasheet, PDF (913/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 23 I/O Ports
23.9.2 Port J Data Register (PJDR)
PJDR is a 13-bit readable/writable register with three reserved bits that stores data for pins PTJ12
to PTJ0. The PJDR is initialized to H'0000 by a power-on reset, but it retains its previous value by
a manual reset, in standby mode, or in sleep mode.
Bit
Bit Name
15 to 13 
12
PJ12DT
11
PJ11DT
10
PJ10DT
9
PJ9DT
8
PJ8DT
7
PJ7DT
6
PJ6DT
5
PJ5DT
4
PJ4DT
3
PJ3DT
2
PJ2DT
1
PJ1DT
0
PJ0DT
Initial
Value
All 0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Bits PJ12DT to PJ0DT correspond to pins PTJ12 to
R/W ^{PTJ0. When the pin function is general output port, the}
value of the corresponding bit in PJDR is returned
R/W _{directly by reading the port. When the function is}
R/W ^{general input port, the corresponding pin level is read}
by reading the port. Table 23.12 shows the function of
R/W _PJDR.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 23.12 Port J Data Register (PJDR) Read/Write Operations
PJnMD2 PJnMD1 Pin State
Read
Write
0
0
Input
Pin state
Data is written to PJDR, but does not affect
pin state.
1
Output
PJDR value Data is written to PJDR and the value is
output from the pin.
1
0
Reserved


1
Other functions Pin state Data is written to PJDR, but does not affect
pin state.
(n = 0 to 12)
Rev. 4.00 Sep. 14, 2005 Page 863 of 982
REJ09B0023-0400