SH7641 Datasheet, PDF (982/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
25.3.5 Bus Cycle of Byte-Selection SRAM
CKIO
A25 to A0
Th
T1
Twx
T2
Tf
t_AD1
t_AD1
t_CSD1
t_CSD1
CSn
WEn
t_RWD1
t_WED1
t_WED1
t_RWD1
RD/WR
t_RSD
t_RSD
Read
RD
D31 to D0
RD/WR
Write
D31 to D0
BS
DACKn,
TENDn*
t_RWD1
t_WDD1
t_BSD
t_DACD
t_BSD
t_WTH1
t_WTH1
t_RDS1
t_RDH1
t_RWD1
t_WDH1
t_DACD
WAIT
t_WTS1
t_WTS1
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One
Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
Rev. 4.00 Sep. 14, 2005 Page 932 of 982
REJ09B0023-0400