SH7641 Datasheet, PDF (276/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.3.3 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to
IRQ0 individually: rising edge, falling edge, high level, or low level. This register is initialized to
H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Initial
Bit
Bit Name Value R/W Description
15

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
14
IRQE*
1
R/W Interrupt Request Enable
Enables or disables the use of pins IRQ7 to IRQ0 as
eight independent interrupt pins.
0: Use of pins IRQ7 to IRQ0 as eight independent
interrupt pins enabled*
1: Use of pins IRQ7 to IRQ0 as interrupt pins disabled
13, 12 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
11
IRQ51S
0
R/W IRQn Sense Select
10
IRQ50S
0
9
IRQ41S
0
8
IRQ40S
0
7
IRQ31S
0
6
IRQ30S
0
5
IRQ21S
0
4
IRQ20S
0
3
IRQ11S
0
2
IRQ10S
0
1
IRQ01S
0
0
IRQ00S
0
R/W These bits select whether interrupt request signals
R/W ^{corresponding to pins IRQ5 to IRQ0 are detected by a}
rising edge, falling edge, high level, or low level.
R/W
Bit 2n+1 Bit 2n
R/W
IRQn1S IRQn0S
R/W
0
0
: Interrupt request is detected on falling
R/W
edge of IRQn input
R/W ₀
1
: Interrupt request is detected on rising
R/W
edge of IRQn input
R/W 1
R/W
R/W ¹
0
: Interrupt request is detected on low
level of IRQn input
1
: Interrupt request is detected on high
level of IRQn input
n = 0 to 5
Note: * The IRQE bit must be cleared to 0 in the initialization routine after a reset, and must then
not be changed.
Rev. 4.00 Sep. 14, 2005 Page 226 of 982
REJ09B0023-0400