SH7641 Datasheet, PDF (394/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(3)
Setting
BSZ
1, 0
A2/3
ROW
1, 0
A2/3
COL
1, 0
11 (32 bits) 00 (11 bits)
00 (8 bits)
Output Pin of Row Address Column Address SDRAM Pin
This LSI
Output Cycle Output Cycle
Function
A17
A26
A17
A16
A25*²*³
A25*²
A15
A24*²
A24*²
A14 (BA1)
A13 (BA0)
Unused
Specifies bank
A14
A23
A14
A12
Address
A13
A22
A13
A11
A12
A21
L/H*¹
A11
A20*²
A11
A10/AP
A9
Specifies
address/precharge
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
Unused
A0
A9
A0
Example of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 9 bits product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A 25 pin specified the bank address.
RASU is not asserted.
Rev. 4.00 Sep. 14, 2005 Page 344 of 982
REJ09B0023-0400