SH7641 Datasheet, PDF (807/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
20.3.11 USBEP0s Data Register (USBEPDR0s)
USBEPDR0s is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception and
stores an 8-byte command data that is sent in the setup stage. USBEPDR0s receives only
commands requiring processing on the microcomputer (firmware) side. Commands that this
module automatically processes are not stored. When command data is received normally, the
SETUPTS bit in USB interrupt flag register 0 is set.
As a setup command must be received without fail, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority and the read data is invalid.
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value
R/W
Undefined R
Description
Register for storing the setup command on control
OUT transfer
20.3.12 USBEP1 Data Register (USBEPDR1)
USBEPDR1 is a 128-byte receive FIFO buffer for endpoint 1. USBEPDR1 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When one packet of data is
received normally from the host, the EP1FULL bit in USB interrupt flag register 0 is set. The
number of receive bytes is indicated in the EP1 receive data size register. After the data has been
read, the buffer that was read is enabled to receive again by writing 1 to the EP1RDFN bit in the
USB trigger register. The receive data in this FIFO buffer can be transferred by DMA (dual
address transfer byte by byte).
USBEPDR1 can be initialized by means of the EP1CLR bit in USBFCLR.
Initial
Bit
Bit Name Value
R/W
31 to 0* D31 to D0 Undefined R
Note: * 7 to 0 bits for DMA transfer.
Description
Data register for endpoint 1 transfer
Rev. 4.00 Sep. 14, 2005 Page 757 of 982
REJ09B0023-0400