SH7641 Datasheet, PDF (733/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Release from High-Impedance State: High-current pins that have entered high-impedance state
due to input-level detection can be released either by returning them to their initial state with a
power-on reset, or by clearing all of the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-
current pins that have become high-impedance due to output-level detection can be released either
by returning them to their initial state with a power-on reset, or by first clearing bit 9 (OCE) of the
OCSR to disable output-level compares, then clearing the bit 15 (OSF) flag. However, when
returning from high-impedance state by clearing the OSF flag, always do so only after outputting a
high level from the high-current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and
TIOC4D). High-level outputs can be achieved by setting the MTU internal registers.
Rev. 4.00 Sep. 14, 2005 Page 683 of 982
REJ09B0023-0400