SH7641 Datasheet, PDF (456/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
can be set independently.
Figure 13.1 shows the block diagram of the DMAC.
X/Y memory
On-chip
peripheral module
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
Iteration
control
Register
control
DMAC module
SAR_n
DAR_n
DMATCR_n
Start-up
control
Request
priority
DEIn
control
CHCR_n
DMAOR
DMARS0,1
External ROM
External RAM
Bus
interface
External device
(memory mapped)
External device
(with acknowledge-
ment)
Bus state
controller
DACK0, DACK1
TEND
DREQ0 , DREQ1
[Legend]
SAR_n: DMA source address register
DAR_n: DMA destination address register
DMATCR_n: DMA transfer count register
CHCR_n: DMA channel control register
DMAOR: DMA operation register
DMARS0,1: DMA extension resource selector
DEIn:
DMA transfer end interrupt request to the CPU
n:
0, 1, 2, 3
Figure 13.1 Block Diagram of the DMAC
Rev. 4.00 Sep. 14, 2005 Page 406 of 982
REJ09B0023-0400