SH7641 Datasheet, PDF (149/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
Section 3 DSP Operation
3.1 Data Operations of DSP Unit
3.1.1 ALU Fixed-Point Operations
Figure 3.1 shows the ALU arithmetic operation flow. Table 3.1 shows the variation of this type of
operation and table 3.2 shows the correspondence between each operand and registers.
39 31
0 39 31
0
Guard _{Source 1}
Guard Source 2
ALU
GT Z N V DC
DSR
Guard Destination
39 31
0
Figure 3.1 ALU Fixed-Point Arithmetic Operation Flow
Note:
The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
ALU fixed-point operations are executed between registers. Each source and destination
operand are selected independently from one of the DSP registers. When a register
providing guard bits is specified as an operand, the guard bits are activated for this type of
operation. These operations are executed in the DSP stage, as shown in figure 3.2. The
DSP stage is the same stage as the MA stage in which memory access is performed.
Rev. 4.00 Sep. 14, 2005 Page 99 of 982
REJ09B0023-0400