SH7641 Datasheet, PDF (206/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 5 Watchdog Timer (WDT)
Figure 5.1 shows a block diagram of the WDT.
Standby
cancellation
Standby
control
WDT
Internal
reset
request
Interrupt
request
Reset
control
Interrupt
control
Divider
Clock selection
Overflow
Clock selector
Clock
WTCSR
WTCNT
Bus interface
[Legend]
WTCSR:Watchdog timer control/status register
WTCNT:Watchdog timer counter
Figure 5.1 Block Diagram of the WDT
Standby
mode
Peripheral
clock
5.2 Register Descriptions
The WDT has the following two registers. See section 24, List of Registers, for the addresses and
access sizes of these registers.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
5.2.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit readable/writable register that is incremented by
cycles of the selected clock signal. When an overflow occurs, it generates a reset in watchdog
timer mode and an interrupt in interval timer mode. The WTCNT counter is initialized to H'00
only by a power-on reset caused by the RESETP pin. Use a word access to write to the WTCNT
counter, writing H'5A in the upper byte. Use a byte access to read the WTCNT.
Note: The WTCNT differs from other registers in the prevention of erroneous writes.
See section 5.2.3, Notes on Register Access, for details.
Rev. 4.00 Sep. 14, 2005 Page 156 of 982
REJ09B0023-0400