SH7641 Datasheet, PDF (1003/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11*¹
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
Tp
Tpw
Trr
t_AD3
t_AD3
t_AD3
t_AD3
t_CSD2
t_CSD2
t_CSD2
t_CSD2
t_RWD2
t_RWD2
t_RASD2 t_RASD2
t_RASD2 t_RASD2
t_CASD2
t_DQMD2
t_CASD2 t_CASD2
(Hi-Z)*³
Trc
Trc
Trc
BS
CKE
t_CKED2
t_CKED2
DACKn,
TENDn*²
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn and TENDn when active low is selected.
3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
(WTRP = 2 Cycles)
Rev. 4.00 Sep. 14, 2005 Page 953 of 982
REJ09B0023-0400