SH7641 Datasheet, PDF (603/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value R/W Description
0
TGFA
0
R/(W) Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFA after reading TGFA = 1
For DMA, 0 must not be written to after reading
TGFA = 1. This flag is cleared only by hardware.*
Note: Write 0 after reading TGFA=1 only when a DMA address error occurs during a DMA read
cycle.
18.3.6 Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a power-on reset and in standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
18.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3,
and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be
designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;
they must always be accessed in 16-bit units. TGR buffer register combinations are TGRA to
TGRC and TGRB to TGRD.
Rev. 4.00 Sep. 14, 2005 Page 553 of 982
REJ09B0023-0400