SH7641 Datasheet, PDF (96/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Table 2.7 T Bit
This LSI's CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
#–1,R0
CMP/EQ #0,R0
BT
TRGET
Description
If R0 ≥ R1, the T bit is set.
A branch is made to TRGET0
if R0 ≥ R1, or to TRGET1 if R0 < R1.
The T bit is not set by ADD.
If R0 = 0, the T bit is set.
A branch is made if R0 = 0.
Example of Other CPU
CMP.W R1,R0
BGE
TRGET0
BLT
TRGET1
SUB.W #1,R0
BEQ
TRGET
Immediate Data: Byte immediate data is placed inside the instruction code. Word and longword
immediate data is not placed inside the instruction code, but in a table in memory. The table in
memory is referenced with an immediate data transfer instruction (MOV) using PC-relative
addressing mode with displacement.
Table 2.8 Immediate Data Referencing
Type
This LSI's CPU
8-bit immediate
MOV
#H'12,R0
16-bit immediate
MOV.W @(disp,PC),R0
........
.DATA.W H'1234
32-bit immediate
MOV.L
@(disp,PC),R0
........
.DATA.L H'12345678
Note: Immediate data is referenced by @(disp,PC).
Example of Other CPU
MOV.B #H'12,R0
MOV.W #H'1234,R0
MOV.L
#H'12345678,R0
Absolute Addresses: When data is referenced by an absolute address, the absolute address value
is placed in a table in memory beforehand. Using the method whereby immediate data is loaded
when an instruction is executed, this value is transferred to a register and the data is referenced
using register indirect addressing mode.
Rev. 4.00 Sep. 14, 2005 Page 46 of 982
REJ09B0023-0400