SH7641 Datasheet, PDF (848/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 21 A/D Converter
21.1.1 Block Diagram
Figure 21.1 shows a block diagram of the A/D converter.
AVcc and AVss for both A/D modules are common pins in the chip.
A/D converter 0
Peripheral data bus
Internal
data bus
AV_CC
AV_SS
10 bit
A/D
AN0
+
AN1
Analog
AN2
multi
plecer
AN3
–
Comparator
Sample and-
hold circuit
Control circuit
A/D converter 1
Peripheral data bus
MTU
trigger
ADI0
interrupt
signal
Internal
data bus
ADCR
AV_CC
AV_SS
10 bit
A/D
AN4
+
AN5
Analog
AN6
multi
plecer
AN7
–
Comparator
Sample and-
hold circuit
[Legend]
ADCSR 0: A/D 0 control/status register
ADDRA 0: A/D 0 data register A
ADDRB 0: A/D 0 data register B
ADDRC 0: A/D 0 data register C
ADDRD 0: A/D 0 data register D
ADCR: A/D0, A/D1 control register
Control circuit
ADI1
interrupt
signal
ADCSR 1: A/D 1 control/status register
ADDRA 1: A/D 1 data register A
ADDRB 1: A/D 1 data register B
ADDRC 1: A/D 1 data register C
ADDRD 1: A/D 1 data register D
Figure 21.1 Block Diagram of A/D Converter
Rev. 4.00 Sep. 14, 2005 Page 798 of 982
REJ09B0023-0400