SH7641 Datasheet, PDF (171/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
Pointer (R2, R3, R4, R5)
LAB [31:0]
–4, 0, +4, +R8
Any memory areas
LDB [31:0]
X0
Y0
X1
Y1
A0
M0
A1
M1
A0G A1G DSR
Cannot be specified
Figure 3.16 Single Data-Transfer Operation Flow (Longword)
All data transfer operations are executed in the MA stage of the pipeline.
All data transfer operations do not update any condition code bits in DSR.
Rev. 4.00 Sep. 14, 2005 Page 121 of 982
REJ09B0023-0400