SH7641 Datasheet, PDF (389/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected
without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in
CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 12.8 to 12.13 show the relationship
between the settings of bits BSZ1 and BSZ0, AxROW[1:0], and AxCOL[1:0] and the bits output
at the address pins. Do not specify those bits in the manner other than this table, otherwise the
operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of
address are always output at these pins.
When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word
address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of
SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0
= B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of
SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
Rev. 4.00 Sep. 14, 2005 Page 339 of 982
REJ09B0023-0400