SH7641 Datasheet, PDF (1008/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 25 Electrical Characteristics
25.3.11 I²C Module Signal Timing
Table 25.12 I²C Bus Interface Timing
Normal Conditions: V_CC = 1.8 V ± 5%, AV_CC = V_CCQ = 3.0 V to 3.6 V, V_SS = AV_SS = V_SSQ = 0 V,
Ta = −40°C to +85°C
Specifications
Item
Symbol Test Conditions Min.
Typ. Max.
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rising time
SCL, SDA input falling time
SCL, SDA input spike pulse
removal time*²
t_SCL
t_SCLH
t
SCLL
t_SR
t
SF
t_SP
12 t_Pcyc + 600
—
3 t_Pcyc + 300
—
5 t + 300
—
Pcyc
—
—
—
—
—
—
SDA input bus free time
Start condition input hold time
Retransmit start condition input
setup time
t
BUF
t
STAH
t_STAS
5 t_Pcyc
—
3t
—
Pcyc
3t
—
Pcyc
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
t
STOS
t_SDAS
t_SDAH
Cb
3t
—
Pcyc
1 t + 20
—
Pcyc
0
—
0
—
SCL, SDA output falling time
t
SF
V Q = 3.0 to 3.6 V —
CC
—
Note: 1. Pcyc indicates peripheral clock cycle.
2. Depends on the value of the register NF2CYC.
3. Indicates the I/O buffer characteristic.
—
—
—
300
300
1.2
—
—
—
—
—
—
400
250*³
Unit Figure(s)
ns 25.50
ns
ns
ns
ns
t *¹
Pcyc
t_Pcyc
t
Pcyc
t
Pcyc
t
Pcyc
ns
ns
pF
ns
Rev. 4.00 Sep. 14, 2005 Page 958 of 982
REJ09B0023-0400