SH7641 Datasheet, PDF (653/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
TGR_4
Initial output
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT_3, 4 count start
(TSTR setting)
Figure 18.39 Example of Initial Output in Complementary PWM Mode (2)
Rev. 4.00 Sep. 14, 2005 Page 603 of 982
REJ09B0023-0400