SH7641 Datasheet, PDF (260/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
9.4 Exception Processing While DSP Extension Function is Valid
When the DSP extension function is valid (the DSP bit of SR is set to 1), some exception
processing acceptance conditions or exception processing may be changed.
9.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception
In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is
executed when the DSP bit of SR is cleared to 0 (in a mode other than the DSP mode), an illegal
instruction exception occurs.
9.4.2 Exception in Repeat Control Period
If an exception is requested or an exception is accepted during repeat control, the exception may
not be accepted correctly or a program execution may not be returned correctly from exception
processing that is different from the normal state. These restrictions may occur from repeat
detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section,
this period is called the repeat control period.
The following shows program examples where the number of instructions in the repeat loop are 4
or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction
address are described as RPTDTCT. The first, second, and third instructions following the repeat
detection instruction are described as RptDtct1, RptDtct2, and RptDtct2. In addition, [A], [B],
[C1], and [C2] in the following examples indicate instructions where a restriction occurs.
Table 9.3 summarizes the instruction positions and restriction types.
Table 9.3 Instruction Positions and Restriction Types
Instruction
Position
SPC*¹
Illegal
Instruction*²
Interrupt,
Break*³
CPU Address
Error*⁴
[A]
[B]
Retained
[C1]
Added
Retained
Instruction/data
[C2]
Illegal
Added
Retained
Instruction/data
Notes: 1. A specific address is specified in the SPC if an exception occurs while SR.RC[11:0] ≥2.
2. There are a greater number of instructions that can be illegal instructions while
SR.RC[11:0] ≥1.
3. An interrupt break or DMA address error request is retained while SR.RC[11:0] ≥1.
4. A specific exception code is specified while SR.RC[11:0] ≥1.
Rev. 4.00 Sep. 14, 2005 Page 210 of 982
REJ09B0023-0400