SH7641 Datasheet, PDF (292/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 11 User Break Controller (UBC)
Figure 11.1 shows a block diagram of the UBC.
Access
ASID Control
XAB/YAB
IAB LAB
Access
comparator
Address
comparator
ASID
comparator
Channel A
BBRA
BARA
BAMRA
BASRA
Internal bus
Access
comparator
Address
comparator
ASID
comparator
Data
comparator
Channel B
PC trace
CONTROL
BBRB
BARB
BAMRB
BASRB
BBRB
BDMRB
BETR
BRSR
BRDR
BRCR
LDB/IDB/
XDB/YDB
CPU state
signals
[Legend]
BBRA: Break bus cycle register A
BARA: Break address register A
BAMRA: Break address mask register A
BASRA: Break ASID register A
BBRB: Break bus cycle register B
BARB: Break address register B
BAMRB: Break address mask register B
User break request
UBC Location
CCN Location
BASRB: Break ASID register B
BDRB: Break data register B
BDMRB: Break data mask register B
BETR: Break execution times register
BRSR: Branch source register
BRDR: Branch destination register
BRCR: Break control register
Figure 11.1 Block Diagram of User Break Controller
Rev. 4.00 Sep. 14, 2005 Page 242 of 982
REJ09B0023-0400