SH7641 Datasheet, PDF (279/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)
IMR0 to IMR10 are 8-bit readable/writable registers that mask the IRQ and on-chip peripheral
module interrupts. When an interrupt source is masked, interrupt requests may be mistakenly
detected, depending on the operation state of the IRQ pins and on-chip peripheral modules. To
prevent this, set IMR0 to IMR9 while no interrupts are set to be generated, and then read the new
settings from these registers.
Table 10.3 shows the relationship between IMR and each interrupt source.
Initial
Bit
Bit Name Value R/W Description
7
IM7
0
R/W Interrupt Mask
6
IM6
5
IM5
4
IM4
3
IM3
2
IM2
1
IM1
0
IM0
0
R/W Table 10.3 lists the correspondence between the
0
R/W ^{interrupt sources and interrupt mask registers.}
0
R/W ^IMn
0
R/W ^{1: Interrupt source of the corresponding bit is masked.}
0
R/W ^{0: When reading, Interrupt source of the corresponding}
bit is not masked. When writing, No processing.
0
R/W
n = 7 to 0
0
R/W
Rev. 4.00 Sep. 14, 2005 Page 229 of 982
REJ09B0023-0400