SH7641 Datasheet, PDF (1027/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Index
Numerics
16-Bit/32-Bit displacement....................... 47
A
A/D conversion time............................... 810
A/D converter ......................................... 797
A/D Converter Characteristics................ 965
Absolute addresses ................................... 46
Absolute Maximum Ratings ................... 907
Access wait control................................. 329
Acknowledge .......................................... 489
Address array.................................. 180, 190
Address map ........................................... 275
Address multiplexing.............................. 339
Addressing modes..................................... 48
A-field....................................................... 64
ALU fixed-point operations...................... 99
ALU integer operations .......................... 104
ALU logical operations........................... 105
Area division........................................... 273
Arithmetic operation instructions ............. 73
Auto-refreshing....................................... 365
Auto-request mode ................................. 426
Bus Cycle of Byte-Selection SRAM....... 932
Bus state controller........................................ 146
Bus State Controller................................ 269
Byte-selection SRAM interface .............. 377
C
Cache ...................................................... 179
Cascaded operation ................................. 574
Clock frequency control circuit............... 145
Clock operating modes ........................... 146
Clock pulse generator ............................. 143
Clock synchronous serial format............. 497
Compare match ....................................... 564
Compare match timer.............................. 509
Compare matches.................................... 514
Complementary PWM mode .................. 591
Control registers........................................ 31
Control transfer ....................................... 768
CPU........................................................... 25
CPU address error ................................... 206
CPU core instructions ............................... 44
Crystal oscillator ..................................... 145
CSn assert period expansion ................... 331
Cycle-steal mode..................................... 436
B
B-field....................................................... 65
Bit synchronous circuit ........................... 507
Boundary scan ........................................ 471
Branch instructions ................................... 77
Buffer operation...................................... 571
Burst mode.............................................. 438
Burst MPX-I/O interface ........................ 382
Burst ROM interface....................... 376, 386
Burst ROM Read Cycle .......................... 934
Bus arbitration ........................................ 399
D
Data alignment ........................................ 321
Data array........................................ 181, 190
Data formats.............................................. 42
Data size.................................................... 44
Data transfer instructions .......................... 71
Data transfer operation............................ 118
DC Characteristics .................................. 910
Deep sleep mode ..................................... 163
Delayed branching .................................... 45
Rev. 4.00 Sep. 14, 2005 Page 977 of 982
REJ09B0023-0400