SH7641 Datasheet, PDF (344/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Bit
5 to 2
1
0
Bit Name

Initial
Value
All 0
HW1
0
HW0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address,
R/W ^{CSn Negation}
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5BWCR
Bit
Bit Name
31 to 22 
Initial
Value
All 0
21
SZSEI
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W MPX-IO Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BBCR are specified as 11. This bit is
valid only when area 5B is specified as MPX-I/O.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus width
selected by A14 or A21 are summarized below.
SZSEL A14 A21 Bus Width
0
0
Not affected
8 bits
0
0
Not affected
16 bits
1
Not affected
0
8 bits
1
Not affected
1
16 bits
Rev. 4.00 Sep. 14, 2005 Page 294 of 982
REJ09B0023-0400