SH7641 Datasheet, PDF (439/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Tables 12.18 to 12.22 lists the minimum number of idle cycles to be inserted for the normal space
interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the
number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS.
Table 12.18 Minimum Number of Idle Cycles between CPU Access Cycles for the Normal
Space Interface
BSC Register Setting
When Access Size is Less than
Bus Width
When Access Size Exceeds Bus Width
CSnWCR. CSnBCR Read to
WM Setting Idle Setting Read
Write to Read to
Write Write
Write
to Read
Contin-
uous
Read*¹
Contin-
uous
Write*¹
Read to
Read*²
Write to Read to
Write*² Write*²
Write to
Read*²
1
0
1/1/1/2 1/1/2/3 3/3/4/5 0/0/0/0 0/0/0/0 0/0/0/0 1/1/1/2 0/0/0/1 3/3/4/5 0/0/0/0
0
0
1/1/1/2 1/1/2/3 3/3/4/5 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/2 1/1/1/1 3/3/4/5 1/1/1/1
1
1
1/1/1/2 1/1/2/3 3/3/4/5 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/2 1/1/1/1 3/3/4/5 1/1/1/1
0
1
1/1/1/2 1/1/2/3 3/3/4/5 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/2 1/1/1/1 3/3/4/5 1/1/1/1
1
2
2/2/2/2 2/2/2/3 3/3/4/5 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/4/5 2/2/2/2
0
2
2/2/2/2 2/2/2/3 3/3/4/5 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/4/5 2/2/2/2
1
4
4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4
0
4
4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/5 4/4/4/4
1
6
6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6
0
6
6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6 6/6/6/6
0, 1
n (n>=8)
n/n/n/n n/n/n/n n/n/n/n n/n/n/n n/n/n/n n/n/n/n n/n/n/n n/n/n/n n/n/n/n n/n/n/n
Notes: The minimum number of idle cycles is described sequentially for Iφ: Bφ (4:1/3:1/2:1/1:1).
1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the
32-bit access cycle when the bus width is 16 bits, and the minimum number of idle
cycles between continuous access cycles during 16-byte transfer
2. Minimum number of idle cycles for other than the above cases
Rev. 4.00 Sep. 14, 2005 Page 389 of 982
REJ09B0023-0400