SH7641 Datasheet, PDF (810/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
Initial
Bit
Bit Name Value R/W Description
2
EP0sRDFN 0
W
EP0s Read Complete
Write 1 to this bit after EP0s command FIFO data has
been read. Writing 1 to this bit enables
transmission/reception of data in the following data
stage. A NACK handshake is returned in response to
transmit/receive requests from the host in the data
stage until 1 is written to this bit.
1
EP0oRDFN 0
W
EP0o Read Complete
Writing 1 to this bit after one packet of data has been
read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet to
be received.
0
EP0iPKTE 0
W
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
20.3.18 USB Data Status Register (USBDASTS)
USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set to 1 when
data is written to the corresponding FIFO buffer and the packet enable state is set. This bit is
cleared when all data has been transmitted to the host.
In the case of dual-FIFO buffer for endpoint 2, this bit is cleared when all data on two FIFOs has
been transmitted to the host.
USBDASTS can be initialized to H'00 by a power-on reset.
Initial
Bit
Bit Name Value R/W Description
7, 6

All 0
R
Reserved
The write value should always be 0.
5
EP3DE
0
R
EP3 Data Present
This bit is set when the endpoint 3 FIFO buffer
contains valid data.
Rev. 4.00 Sep. 14, 2005 Page 760 of 982
REJ09B0023-0400