SH7641 Datasheet, PDF (908/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 23 I/O Ports
Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT,
PG8DT)
PGnMD2 PGnMD1 Pin State
0
0
Input
1
Output
Other than above
(n = 8, 11 to 13)
Reserved
Read
Write
Pin state
Data is written to PGDR, but does not affect
pin state.
PGDR value Data is written to PGDR and the value is
output from the pin.


Table 23.9 Port G Data Register (PGDR) Read/Write Operations (PG10DT to PG9DT)
PGnMD2 PGnMD1 Pin State
Read
Write
0
0
Input
Pin state
Data is written to PGDR, but does not affect
pin state.
1
Output
PGDR value Data is written to PGDR and the value is
output from the pin.
1
0
Reserved


1
Other function Pin state
Data is written to PGDR, but does not affect
pin state.
(n = 9, 10)
Table 23.10 Port G Data Register (PGDR) Read/Write Operations (PG7DT to PG0DT)
PGnMD2
0
1
(n = 0 to 7)
Pin State
Input/other function
(The A/D converter is
used.)
Input/other function
(The A/D converter is
not used.)
Reserved
Read
Prohibited
Pin state

Write
Prohibited
Ignored (does not affect pin state.)

Rev. 4.00 Sep. 14, 2005 Page 858 of 982
REJ09B0023-0400