SH7641 Datasheet, PDF (446/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single
Address Mode for the SDRAM Interface
(1) Transfer from the external device with DACK to the SDRAM interface
CMNCR.DMAIW
Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BSC Register Setting*²
CS3WCR.WTRP
Setting
CS3WCR.TRWL
Setting
0
0
0
1
0
2
0
3
1
0
1
1
1
2
1
3
2
0
2
1
2
2
2
3
3
0
3
1
3
2
3
3
0
0
0
1
0
2
0
3
1
0
1
1
1
2
1
3
2
0
2
1
2
2
2
3
3
0
3
1
Minimum Number of
Idle Cycles
3
3
3
3
3
3
3
4
3
3
4
5
3
4
5
6
3
3
3
3
3
3
3
4
3
3
4
5
3
4
Rev. 4.00 Sep. 14, 2005 Page 396 of 982
REJ09B0023-0400