SH7641 Datasheet, PDF (676/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DMA is activated, the flag is cleared automatically. Figure 18.68 shows the
timing for status flag clearing by the CPU, and figure 18.69 shows the timing for status flag
clearing by the DMA.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 18.68 Timing for Status Flag Clearing by the CPU
Pφ
DMA falg clear
signal
Status falg
DMA transfer
request signal
Figure 18.69 Timing for Status Flag Clearing by DMA Activation
Rev. 4.00 Sep. 14, 2005 Page 626 of 982
REJ09B0023-0400