SH7641 Datasheet, PDF (217/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 6 Power-Down Modes
6.2.2 Standby Control Register 2 (STBCR2)
The standby control register 2 (STBCR2) is a readable/writable 8-bit register that controls the
operation of modules in the power-down mode. STBCR2 is initialized (to H'00) by a power-on
reset but retains its previous value after a manual reset or a period in the standby mode. Only byte
access is valid.
Initial
Bit
Bit Name Value R/W Description
7
MSTP10 0
R/W Module Stop 10
When the MSTP10 bit is set to 1, the supply of the
clock to the H-UDI is halted.
0: H-UDI runs.
1: Clock supply to H-UDI halted.
6
MSTP9
0
R/W Module Stop 9
When the MSTP9 bit is set to 1, the supply of the
clock to the UBC is halted.
0: UBC runs.
1: Clock supply to UBC halted.
5
MSTP8
0
R/W Module Stop 8
When the MSTP8 bit is set to 1, the supply of the
clock to the DMAC is halted.
0: DMAC runs.
1: Clock supply to DMAC halted.
4
MSTP7
0
R/W Module Stop 7
When the MSTP7 bit is set to 1, the supply of the
clock to the DSP is halted.
0: DSP runs.
1: Clock supply to DSP halted.
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Sep. 14, 2005 Page 167 of 982
REJ09B0023-0400