SH7641 Datasheet, PDF (473/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
Transfer requests from the various modules are specified by the MID and RID as shown in table
13.3.
Table 13.3 Transfer Request Module/Register ID
Peripheral Module
SCIF0
SCIF1
SCIF2
MTU0
MTU1
MTU2
MTU3
MTU4
USB
A/D converter 1
CMT1
Setting Value for One
Channel (MID + RID)
H'88
H'89
H'90
H'91
H'40
H'41
H'A8
H'C0
H'C8
H'D0
H'E8
H'A0
H'A1
H'B0
H'F0
MID
RID
B'100010
B'00
B'01
B'100100
B'00
B'01
B'010000
B'00
B'01
B'101010
B'00
B'110000
B'00
B'110010
B'00
B'110100
B'00
B'111010
B'00
B'101000
B'00
B'01
B'101100
B'00
B'111100
B'00
Function
Transmit
Receive
Transmit
Receive
Transmit
Receive
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
Transmit
Receive


When MID/RID other than the values listed in table 13.3 is set, the operation of this LSI is not
guaranteed. The transfer request from the DMARS register is valid only when the resource select
bits (RS3 to RS0) have been set to B'1000 for CHCR0 to CHCR3 registers. Otherwise, even if the
DMARS has been set, transfer request source is not accepted.
Rev. 4.00 Sep. 14, 2005 Page 423 of 982
REJ09B0023-0400