SH7641 Datasheet, PDF (397/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(5)-1
Setting
BSZ
1, 0
A2/3
ROW
1, 0
A2/3
COL
1, 0
11 (32 bits) 00 (11 bits)
00 (8 bits)
Output Pin of Row Address Column Address SDRAM Pin
This LSI
Output Cycle Output Cycle
Function
A17
A26
A17
Unused
A16
A25
A16
A15
A24
A15
A14
A23
A23*²
A13
A22*²
A22*²
A12
A21*²
A12
A11
A20
L/H*¹
A13 (BA1)
A12 (BA0)
A11
A10/AP
Specifies bank
Address
Specifies
address/precharge
A10
A19
A10
A9
Address
A9
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
Unused
Example of connected memory
128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 4.00 Sep. 14, 2005 Page 347 of 982
REJ09B0023-0400