SH7641 Datasheet, PDF (53/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 1 Overview
Items
Cache memory
X/Y memory
Interrupt controller
(INTC)
User break controller
(UBC)
Specification
• 16-kbyte cache, mixed instruction/data
• 256 entries, 4-way set associative, 16-byte block length
• Write-back, write-through, LRU replacement algorithm
• 1-stage write-back buffer
• Maximum 2 ways of the cache can be locked
• Three independent read/write ports
 8-/16-/32-bit access from the CPU
 Maximum two 16-bit accesses from the DSP
 8-/16-/32-bit access from the DMAC
• Total memory: 16-kbyte (XRAM: 8-kbyte, YRAM: 8-kbyte)
• Nine external interrupt pins (NMI, IRQ7 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• Supports soft vector mode
• Addresses, data values, type of access, and data size can all be set
as break conditions
• Supports a sequential break function
• Two break channels
Rev. 4.00 Sep. 14, 2005 Page 3 of 982
REJ09B0023-0400