SH7641 Datasheet, PDF (850/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 21 A/D Converter
21.1.3 Register Configuration
The A/D converter's registers are summarized below.
• A/D0 data register A (ADDRA0)
• A/D0 data register B (ADDRB0)
• A/D0 data register C (ADDRC0)
• A/D0 data register D (ADDRD0)
• A/D0 control/status register (ADCSR0)
• A/D1 data register A (ADDRA1)
• A/D1 data register B (ADDRB1)
• A/D1 data register C (ADDRC1)
• A/D1 data register D (ADDRD1)
• A/D1 control/status register (ADCSR1)
• A/D0 A/D1 control register (ADCR)
21.2 Register Descriptions
21.2.1 A/D Data Registers A to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1)
The eight A/D data registers (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1) are 16-bit read-
only registers that store the results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The 10 bits of the result are stored in the upper bits
(bits 15 to 6) of the A/D data register. Bits 5 to 0 of an A/D data register are reserved bits that are
always read as 0. Table 21.2 indicates the pairings of analog input channels and A/D data
registers.
The A/D data registers are initialized to H'0000 by a power-on reset and in standby mode.
Rev. 4.00 Sep. 14, 2005 Page 800 of 982
REJ09B0023-0400